Some image processing systems use polyphase filters. For example, when video data are broadcast in a high-definition format, it is necessary to convert them into a standard format in order to be able to display them on a television whose screen is not compatible with the high-definition format. A polyphase filter in particular makes it possible to perform such a conversion with good quality.
United States patent U.S. Pat. No. 5,383,155 granted on 17 Jan. 1995 describes several embodiments of polyphase filters. In one of the embodiments, the polyphase filter described is a 64-taps polyphase filter consisting of eight 8-taps polyphase filters placed in series.
FIG. 1 illustrates an 8-taps polyphase filter as described in this patent. This filter comprises registers 101 and 108 and 111 to 118, multipliers for multiplying by coefficients c1 to c8 and an adder 120. This filter functions in direct mode.
Data are received in series one after another by the filter. These data correspond for example to pixel values P1 to P8 of an input image. In addition, a clock controls the registers. At each clock cycle, a data item is received at the register 101. When a data item arrives at the register 101, the data item situated in the register 101 shifts towards the register 102, the data item situated in the register 102 shifts towards the register 103 and so on. Thus, after eight clock cycles, the pixel value P8 is situated in the register 101, the pixel value P7 in the register 102 and so on. The multipliers then calculate values c8*P8, c7*P7 and so on. The adder 120 next calculates a result S:S=c1*P1+c2*P2+c3*P3+c4*P4+c5*P5+c6*P6+c7*P7+c8*P8.
FIG. 2 illustrates a 64-taps polyphase filter as described in U.S. Pat. No. 5,383,155. This filter comprises eight 8-taps polyphase filters 201 to 208, as described in FIG. 1, as well as eight registers 211 to 218. These filters are placed in series, each filter sending to the following filter data to be processed and the results which it has calculated. Assume that the filter in FIG. 1 is the filter 202 in FIG. 2. The adder 120 has an input S(−1) which receives the result calculated by the filter 201 at the previous clock cycle, from eight data items. Thus the filter 202 calculates a result from sixteen data items, the filter 203 from twenty-four data items and so on. The filter 208 therefore calculate a result from sixty-four data items. The registers 211 to 217 serve to ensure that the filters 201 to 208 are correctly put in series.
A drawback of such a filter lies in the fact that it carries out only a polyphase filtering with a fixed number of taps. This is because, once the filters 201 to 208 in FIG. 2 are placed in series, it is no longer possible to carry out a 50-taps polyphase filtering for example.
However, current video processing systems require various types of polyphase filtering, in particular because of the large number of image formats used in television. Consequently, if it is wished to use the teachings of the patent cited above, it is necessary to provide in this circuit as many polyphase filters as there are types of polyphase filtering required. Such a solution has many drawbacks, in particular because these circuits occupy a large surface area of silicon in the circuit.